The present invention relates to a clock switching device mounted on a logic circuit or a processing device using one of a plurality of clock signals each having a different frequency, and to a clock switching method.
The use of IC cards in corporating a microcomputer has been popular. The IC card has outer connection terminals such as a power supply terminal, a clock terminal, a reset terminal, and a serial I/O. Then, the IC card can be accessed by an outer device such as a card reader/writer (hereinafter called reader/writer) through the outer connection terminals.
The clock terminal, which is one of the outer connection terminals, is used to fetch a clock signal for operating the microcomputer in the card.
In some of the IC cards, two clock signals each having a different frequency are fetched sequentially so as to perform a series of operations. In such a case, there is needed a clock switching device for selecting any one of two clock signals to be supplied to the IC card in the reader/writer, in addition to an oscillation circuit for oscillating each clock signal. Following are two examples of the clock switching device:
(1) One clock signal (c1) is input to one input terminal of a two-input AND gate (g1), and a clock selection signal is input to the other input terminal. Another clock signal (c2) is input to one input terminal of another two-input AND gate (g2), and a reverse signal of the clock selection signal is input to the other input terminal through an inverter (g3).
An output of the gate (g1) is supplied to one input terminal of a two-input OR gate (g4), and an output of the gate (g2) is supplied to the other terminal. An output of the gate (g4) is supplied to a system using the clock signal (c1) or (c2).
A method of using this circuit can be as follows:
Specifically, the level of a clock selection signal is switched such that a clock signal to be used is output from the AND gate to which the clock signal is input. Since allowance of the output of two clock signals is designated by one control signal, the collision of two clock signals does not occur in outputting the clock signal to the system to be used. (2) As the other example, clock enable signals (s1) and (s2) are generated and used in place of the clock selection signals.
One clock signal (c1) is input to one input terminal of the two-input AND gate (g1), and the clock enable signal (g2) is input to the other input terminal. The other clock signal (c2) is supplied to one input terminal of the other two-input AND gate (g2), and the clock enable signal (s2) is input to the other input terminal.
The output of the gate (g1) is supplied to one input terminal of the two-input OR gate (g4), and the output of the gate (g2) is supplied to the other terminal. The output of the gate (g4) is supplied to system using the clock signal (c1) or (c2).
The following will explain the case in which the clock signal (c1) is used in this system.
First, the clock enable signals(s1) and (s2) are set to a "clock disable" state to stop the clock output to the system. From this state, the clock enable signal (s1) is set to a "clock enable" state. Thereby, the clock signal (c1) is supplied to the system. For supplying the clock signal (c2) to the system, the clock enable signal (s1) is set to a "clock disable" state. Thereafter, the clock enable signal (s2) is set to a "clock enable" state. Thereby, the clock signal (c2) is supplied to the system.
The following will explain the problems of the above conventional clock switching device.
(a) The clock signals, which are non-synchronous with the clock signals (c1) and (c2), are supplied to the system. In other words, the signals, which are not synchronized with the clock signals (c1) and (c2), are used as clock selection signals or clock enable signals. As a result, there is possibility that pulses, which are not synchronized with the clock signals (1) and (c2), are generated to an output line as noise.
(b) The number of parts to be used is increased to obtain the clock signals, which are synchronized with the clock signals (c1) and (c2).
In other words, to synchronize the clock signals to be supplied to the system with the clock signals (c1) and (c2), there is needed a synchronism circuit using two or more flip flops for each of clock signals (c1) and (c2) (that is, four or more flip flops are needed). The flip flops operate using a clock selection signal as a trigger. Then, current output clock signals (c1) and (c2) are supplied to clock inputs of the flip flop. As a result, the number of parts to be used is increased, the control circuit becomes complicated, and the manufacturing cost is increased.
(c) It takes much time for the signal to be actually switched to the clock signal after the designation of the clock switching.
In the structure using the synchronism circuit described in above item (b), an amount of time, which corresponds to the sum of two cycles of each clock signal, is needed such that a new clock signal is output on an output line after the signal is synchronized with the outputting clock signal and the output of the clock signal is stopped.
(d) The structure using two clock enable signals (s1) and (s2) described in above item (2) is limited in that these clock enable signals (s1) and (s2) are not simultaneously set to the "clock enable" state.